`timescale 1ns/1ns
module tb_SinglePortRam ();

    reg sys_clk;
    reg sys_rst_n;

    // 50MHz的时钟
    always #10 sys_clk=!sys_clk;

    initial begin
        sys_rst_n<=1'b0;
        sys_clk<=1'b0;
        #100;
        sys_rst_n<=1'b1;
    end


    SinglePortRam u_SinglePortRam(
                      .sys_clk   	(sys_clk    ),
                      .sys_rst_n 	(sys_rst_n  )
                  );


endmodule
